1. Field of the Invention
The present invention relates to the field of electronic devices. More specifically, the present invention relates to circuits for protecting such electronic devices from ElectroStatic Discharge (‘ESD’) events.
2. Discussion of the Related Art
Electronic devices, such as semiconductor devices of an Integrated Circuit (‘IC’), need protection against undesired, potentially harmful events. Examples of these undesired events are electrostatic discharges, occurring when an electrostatic charge builds up on one of two electrically insulated elements, like the plates of a capacitor, so as to significantly increase the electrical potential difference between the two elements, until a conductive path from the first to the second insulated element is established, resulting in a sudden and undesired current, which may damage the semiconductor device, e.g. the capacitor dielectric.
Generally, electrostatic discharge takes place during handling of the integrated circuit. For example, damage occurs during the testing phase of the IC, or during its packaging or assembly onto a circuit board, and possibly during the operation of the electronic system of which the IC is part. Damages caused by ESD events can partially or totally hamper the functionality of the IC.
ESD events may, in particular, occur when a charged body (such as a person) touches the externally-accessible terminals of the IC. Each external terminal (which is used for accessing the IC from the outside) is connected, typically through a bonding wire, to a corresponding internal terminal of the IC. In such a way, the ESD event can involve one or more of the semiconductor devices of the IC. For example, a semiconductor device of the IC may be applied a voltage drop higher than a maximum voltage which it is able to sustain, and thus it may break.
In order to avoid damage caused ESD events, ICs comprise ESD protection circuits associated with the IC terminals. In particular, known ESD protection circuits are designed to provide, when necessary, a high conductivity path, adapted to safely sink the excessive electrostatic charge that builds up on the IC internal terminals from the semiconductor devices of the IC.
Examples of ESD protection circuits are well known in the art. An example of known ESD protection circuit, used in particular to protect semiconductor devices which are power device, such as power MOSFETs, adapted to sustain voltages ranging from, for example, 8V to 1500V, includes two circuit branches, arranged in a Π-shaped circuit structure; each branch includes two Zener diodes, which are connected in series and back to back. In case of an ESD event, either one of the two Zener diodes in each branch is reverse biased at the Zener voltage, whereas the other Zener diode is forward biased; the excessive electrostatic charge is thus safely sunk.
For better clarity, a conventional Π-shape ESD protection circuit 105 is schematically shown in FIG. 1. The ESD protection circuit 105 can be schematized as a quadrupole coupled to two IC terminals 106 and 107, in the example herein considered input terminals; for example, the terminal 107 is the IC terminal intended in operation to be connected to a reference voltage, like the ground, whereas the input terminal 106 is a terminal that, in operation, is intended to receive a drive (gate) voltage Vin (with respect to the ground voltage applied to the terminal 107) for a semiconductor device 110 which is assumed to be a power MOSFET. The ESD protection circuit 105 is further coupled to a first and second terminals 108 and 109 of the semiconductor device 110, in the example considered the gate and the source of the power MOSFET to be protected.
ESD events may cause the drive voltage Vin to take values that are much higher than the maximum value it is expected to take in operation, and may be either positive or negative.
In the drawing, the semiconductor device 110 is schematically represented by a capacitor Cgs, representative of the gate capacitance of the power MOSFET, between the power MOSFET gate terminal 108 and source terminal 109. The capacitor Cgs is designed so as to be able to sustain without breaking a voltage difference up to a breaking voltage Vbv (for example, ranging from 15V to 30V).
The protection circuit 105 includes a first circuit branch 111 with two Zener diodes D1 and D2, which are connected back to back (i.e., the diode D1 has a cathode terminal connected to a cathode terminal of the diode D2) in series between a first terminal 113 connected to the IC terminal 106 and a second terminal 114 connected to the IC terminal 107.
The protection circuit 105 has a second circuit branch 112 including two further back-to-back Zener diodes D3 and D4 connected in series between a first terminal 115 and a second terminal 116 of the second branch 112. A resistor R1 is connected between the first terminal 113 of the first circuit branch 111 and the first terminal 115 of the second circuit branch 112. The second terminal 116 of the second circuit branch 112 is connected to the IC terminal 107, so that the first and the second circuit branches 111 and 112 together with the resistor R1 have a Π shape.
In the example at issue, the Zener diodes D1 and D2 are designed so to have a first Zener (breakdown) voltage Vz1 lower in absolute value than the absolute value of the breaking voltage Vbv. In particular, the first Zener voltage Vz1 is lower than the breaking voltage Vbv of at least a predetermined voltage Vf, that corresponds to the diode threshold voltage for entering the forward-biasing condition (e.g., Vf ranges from 0.2V to 0.4V). The Zener diodes D3 and D4 are designed so to have a second Zener (breakdown) voltage Vz2. Typically, the second Zener (breakdown) voltage Vz2 is equal to the first Zener voltage Vz1.
In absence of the protection circuit 105, when, due to an ESD event, the value of the drive voltage Vin exceeds the breaking voltage Vbv (in particular, when the value of the drive voltage is approximately an order of magnitude higher than the breaking voltage Vbv, such as, from 2000V to 8000V according to the IEC 1000-4-2 specification relating to the ESD protection levels) a discharge current Ibv would flow through the capacitor Cgs, which would thus be damaged. In cases like this, the ESD protection circuit 105 activates to safely sink from the capacitor Cgs the discharge current Ibv, and limiting the voltage applied to the semiconductor device 110.
In fact, in such biasing condition, depending on the polarity (sign) of the drive voltage Vin, one between the Zener diodes D1 and D2 conducts a reverse current, being reverse biased at the first Zener voltage, whereas the other Zener diode is forward biased and thus conducts a forward current.
In particular, when the drive voltage Vin is positive (with the sign convention adopted in FIG. 1 i.e., the potential at the IC terminal 106 is higher than the potential at the IC terminal 107 of at least the first Zener voltage Vz1 plus the diode threshold voltage value Vf), the diode D1 is forward biased, whereas the diode D2 is reverse biased at the first Zener voltage Vz1. As a result, a first current I111 flows through the first circuit branch 111 from the first terminal 113 to the second terminal 114 thereof.
Concurrently, the diodes D3 and D4 conduct current, being the diode D3 forward biased and the diode D4 reverse biased, so that the second circuit branch 112 can conduct a second current I112, flowing through the second circuit branch 112 from the first terminal 115 to the second terminal 116 thereof.
Vice versa, when polarity of the drive voltage Vin is reversed (i.e., the IC terminal 106 is at a potential lower than the potential of the IC terminal 107 of at least the first Zener voltage Vz1 plus the diode threshold voltage, the diode D1 is reverse biased at the Zener voltage, whereas the diode D2 is forward biased. The first currents I111 flows in this case through the circuit branch 111 from the second terminal 114 to the first terminal 113 thereof. Similarly, the second current I112 flows through the second circuit branch 112 from the second terminal 116 to the first terminal 115 thereof.
In both cases, substantially no current flows through the semiconductor device 110. The ESD protection circuit thus avoids breaking of capacitor Cgs thus meaning that the gate oxide of the MOSFET is shielded from undesired breaking events.
During the normal operation (when no ESD events occur) the ESD protection circuit 105 is off: as long as the drive voltage Vin is lower than breaking voltage Vbv, the first circuit branch 111 and the second circuit branch 112 are not conductive, since the voltage drop applied thereto is not sufficient for turning on at least one Zener diode among the diodes D1-D4 in reverse biasing voltage operation. In this way, a non-destructive current (i.e., lower in absolute value than the discharge current Ibv) can flow through the semiconductor device 110 for driving it, without causing malfunctioning or damage thereof.